Several types of processing systems have been proposed in the last years in order to obtain high performance. A known solution consists in using a multiprocessor system with a shared memory, wherein several processors execute different operations simultaneously. Typically, each processor includes a cache memory, very fast but with a low capacity, wherein some data blocks stored in the relatively slow shared memory are copied, in such a way as to statistically reduce the number of accesses to the shared memory.
A particular kind of multiprocessor system, described for example in EP-A-0608663, is provided with a plurality of data buses (to each one some processors are connected); the data buses and the shared memory are selectively connected in pairs by means of a cross-bar unit, so that a higher transfer rate on the data buses can be obtained. Each transaction executed in the system includes an address-phase (in which a target unit, either a processor or the shared memory, is selected by a requesting unit) and a data-phase (in which a data block is sent to or received from the target unit). The data-phase is synchronous with the corresponding address-phase; for example, when a processor requests the reading of a data block from the shared memory, this data block is provided to the requesting processor during a fixed time interval (with respect to the beginning of the respective address-phase).
To ensure the consistency of the data blocks of the shared memory replicated in the cache memories, the processors continuously observe (by a technique known as “snooping”) the transaction requests, to check whether the requested data block is present in their cache memory. If the requested data block is present in the cache memory of a processor in a form which is modified with respect to the (no longer valid) value present in the shared memory, this processor intervenes by supplying the modified data block to the requesting processor. In this case, the cross-bar unit can directly connect the data bus of the intervening processor to the data bus of the requesting processor.
In a different type of multiprocessor system with a cross-bar unit, described for example in EP-A-0923032, the data-phase is distinct and temporally unrelated with the corresponding address-phase, so that the data blocks can be supplied to the requesting processor in any sequence. Each data block is provided with a tag which identifies the requesting processor and the corresponding transaction. In this case, when the intervening processor sends the modified data block to the cross-bar unit, the modified data block must be received and stored into an input buffer. Only when the modified data block is available in the cross-bar unit, the cross-bar unit can request an access to the data bus of the requesting processor, according to the identifying tag associated with the modified data block. As soon as the access is granted, the modified data block is sent onto the data bus of the requesting processor.
This document also proposes to grant the access to the data bus of the requesting processor to the cross-bar unit as soon as it is recognised that the requested data block is present in modified form in the cache memory of another processor. Therefore, when the modified data block is stored into the input buffer of the cross-bar unit, this modified data block can be immediately sent onto the data bus of the requesting processor (without waiting for the cross-bar unit to request and to be granted the access to the data bus). Such feature reduces the duration of the transfer of the modified data block from the intervening processor to the requesting processor.
This solution keeps the data bus of the requesting processor busy until the modified data block is supplied by the intervening processor. Alternatively, the document EP-A-0923032 also proposes to grant-a conditional access to the data bus of the requesting processor to the cross-bar unit. In other words, the cross-bar unit is notified of any different request of access to the data bus of the requesting processor before completion of an intervention transaction; the cross-bar unit can decide then, according to the state of the intervention transaction, whether to maintain or to release the access to the data bus of the requesting processor. However, this structure requires further signals to be exchanged and then the use of more dedicated lines.